Computer components generally use a bus, a path, or a point-to-point connection to transfer a request, a command, data, and the like. When a transferred request or command carries an address, address information accounts for a certain proportion in total transferred information.
Due to locality of a program, an address requested in an execution process of the program presents some spatial or temporal locality. Spatial locality is the addresses that the program requires to access converge in a continuous area, which is manifested as address continuity; and temporal locality is that the program requires access to an address for many times within a period of time, which is manifested as address repeatability.
In the execution process of a program, for each request of the program, if a complete address is transferred over a connection without using a feature of locality according to the program itself, transfer of redundant information, a waste of physical bandwidth, and unnecessary transmission power consumption will result. In addition, for a 32-bit central processing unit (CPU), only addresses of at most 32 bits can be transferred, which leads to maximally fourth generation (4G) system memory and limits the capacity of system memory.
In the prior art, two technologies that use temporal locality or spatial locality to perform address compression are as follows.
(1) Dynamic base register caching technology that uses temporal locality of an address: As shown in FIG. 1, an address sent from processor A to processor B is divided into two parts: a high-order part and a low-order part. The low-order part is directly transferred from processor A to processor B. Before being transferred, the high-order part is searched for in a base register cache of processor A, and if not found, the high-order part is stored in the base register cache, and then a storage location label of the high-order part in the base register cache is transferred to a base register array of processor B; and if the high-order part is found in the base register cache of processor A, a location label of the high-order part in the base register cache is directly transferred to the base register array of processor B. An address stored in a base register cache of processor A keeps synchronized with an address stored in the base register array of processor B. Therefore, after the base register array of processor B receives the location label, the high-order part of the address is found in the base register array according to the location label; and finally, the high-order part is transferred to processor B after being read from the base register array.
Due to address repeatability, a length of the high-order part may be set to be relatively long, so that the location label of the high-order part in the base register cache is shorter than the length of the high-order part; therefore, the technology shortens a length of the transferred address.
(2) Stride address compression technology that uses spatial locality of an address: As shown in FIG. 2, an address sent from processor C to processor D is divided into two parts: a high-order part and a low-order part. Before the address is transferred, a difference between the address and an address stored in base register C is obtained, and then the difference is transferred to processor D at a receiving end, and processor D adds the difference and an address stored in base register D to restore an original address. The address stored in base register C keeps synchronized with the address stored in base register D. Because the difference is generally shorter than the original address, the technology shortens a length of the transferred address.
However, a processed unit of both dynamic base register caching and stride address compression technologies is a request, which results that a compression ratio of a transferred address is still not high.